MT47H128M8CF-25:H Micron Technology Inc, MT47H128M8CF-25:H Datasheet - Page 115

no-image

MT47H128M8CF-25:H

Manufacturer Part Number
MT47H128M8CF-25:H
Description
IC DDR2 SDRAM 1GBIT 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet

Specifications of MT47H128M8CF-25:H

Organization
128Mx8
Density
1Gb
Address Bus
17b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
125mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (128M x 8)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-TFBGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT47H128M8CF-25:H
Manufacturer:
MICRON31
Quantity:
4 189
Part Number:
MT47H128M8CF-25:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT47H128M8CF-25:H
Manufacturer:
MICRON
Quantity:
10 000
Company:
Part Number:
MT47H128M8CF-25:H
Quantity:
100
Part Number:
MT47H128M8CF-25:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT47H128M8CF-25:H TR
Manufacturer:
MICRON
Quantity:
8 000
REFRESH
Figure 67: Refresh Mode
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DQS, DQS# 4
Command
Address
Bank
DM 4
DQ 4
CK#
CKE
A10
CK
NOP 1
T0
Notes:
One bank
All banks
Bank(s)
PRE
T1
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-
terval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
t
ceeds +85°C.
RFC (MIN) later. The average interval must be reduced to 3.9µs (MAX) when T
3
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
2. The second REFRESH is not required and is only shown as an example of two back-to-
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
t CK
ble at these times. CKE must be active during clock positive transitions.
back REFRESH commands.
active (must precharge all active banks).
NOP 1
T2
t CH
t RP
t CL
NOP 1
T3
115
REF
T4
t RFC (MIN)
NOP 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ta0
1Gb: x4, x8, x16 DDR2 SDRAM
REF 2
Ta1
Indicates a break in
time scale
NOP 1
Tb0
© 2004 Micron Technology, Inc. All rights reserved.
t RFC 2
NOP 1
Tb1
Don’t Care
REFRESH
C
ex-
Tb2
ACT
RA
RA
BA

Related parts for MT47H128M8CF-25:H