IDT49C466PQF IDT, Integrated Device Technology Inc, IDT49C466PQF Datasheet - Page 11

• Manufacturer Part Number: IDT49C466PQF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT49C466PQF

• Lead Free Status / Rohs Status: Not Compliant

DIAGNOSTIC OUTPUT DATA FORMAT
* Bit #28 = 1 If "Error" condition
Diagnostics
provide error logging information. These include the checkbit register, error
count register, error type register, two syndrome registers and the error
data register. Data is clocked into each of these registers by SYNCLK. The
error data register, checkbit register, error type register and one of the
syndrome registers are reloaded only in the case of the first error after a
clear. The other syndrome register and the error count register are
reloaded on every error condition SYNCLK edge. The contents of the Error
Data register can be read only in Error Data Output mode. The contents of
the other diagnostic registers as well as the checkbit latch can be read in
Diagnostic Output mode.
Parity
memory read the EDC generates parity bits for each data byte and outputs
the parity byte on the parity bus, P0-7. During a memory write, parity is
checked by comparing the parity bits input on P0-7 and the parity bits
generated from the input data word. A discrepancy between these two
causes the PERR flag to be asserted. In the case of partial word writes, the
PERR flag is based on the parity bits Px and data bytes input on SD bus.
IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
Bit #29 = 1 If "Multiple bit Error" condition
37
The diagnostic ability of the IDT49C466 rests on a set of 6 registers that
The IDT49C466 provides a parity check and generation facility. On a
36
(o n every error)
35
Syn drom e
34
33
32
31
30
29
E rro r
error
o nly)
T ype
Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode
(on
1st
28
27
BE 0-7
C o u nt
26
Erro r
F R O M D IAG N O S TIC R E G ISTE R S
25
24
M ODE BIT 0
W FIFO
23
22
(on 1st error)
21
S yn d ro m e
20
T O S D B U S
19
11
18
BE0-7
17
REG ISTER
CHECKBIT
SYN DRO M E
(O n 1st ERR)
ERR CNT
ERR TYPE
SYN DRO M E
(O n every
ERRO R )
64
16
DIAG.
Error Data Regs.
Diag. R egs.
15
(on 1st error o nly)
14
CLE AR
13
W B SE L
C heckbit
12
SYN CLK
LO ADED
SYN CLK
SYN CLK
SYN CLK
SYN CLK
SYN CLK
BY
11
COMMERCIAL TEMPERATURE RANGE
10
↑
↑
↑
↑
↑
9
8
O NLY O N 1st
ERRO R
O NLY O N 1st
ERRO R
O N EVERY
ERROR (Up to
15 ERRO R S)
O NLY O N 1st
ERRO R
O N EVERY
ERRO R
CONDITIO N
7
(fro m ch eckbit latch )
6
C heckbit
5
4
3
SD8-15
SD16-23
SD24-27
SD28-29
SD30-37
O UTPU T
2
1
0