LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 174
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
The Single Port RAM (RAM_DQ) can be configured as NORMAL, READ BEFORE WRITE or WRITE THROUGH
modes. Each of these modes affects what data comes out of the port Q of the memory during the write operation
followed by the read operation at the same memory location. The READ BEFORE WRITE attribute is supported for
x9, x18 and x36 data widths.
Additionally users can select to enable the output registers for RAM_DQ. Figures 8-7 through 8-12 show the inter-
nal timing waveforms for the Single Port RAM (RAM_DQ) with these options.
Figure 9-9. Single Port RAM Timing Waveform – NORMAL Mode, without Output Registers
ClockEn
Address
Clock
WrEn
Data
Q
t
t
SUADDR_EBR
SUDATA_EBR
t
SUCE_EBR
Data_0
Add_0
t
SUWREN_EBR
t
t
HADDR_EBR
HDATA_EBR
Invalid Data
Data_1
Add_1
t
HWREN_EBR
9-9
Add_0
LatticeECP/EC and LatticeXP Devices
t
CO_EBR
Data_0
Add_1
Memory Usage Guide
Data_1
Add_2
t
HCE_EBR
Data_2
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