LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 343
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LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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HDL Synthesis Coding Guidelines
Lattice Semiconductor
for Lattice Semiconductor FPGAs
Implementation of Memories
Although an RTL description of RAM is portable and the coding is straightforward, it is not recommended because
the structure of RAM blocks in every architecture is unique. Synthesis tools are not optimized to handle RAM imple-
mentation and thus generate inefficient netlists for device fitting. For Lattice Semiconductor FPGA devices, RAM
blocks should be generated through IPexpress as shown in the following screen shot.
When implementing large memories in the design, it is recommended to construct the memory from the Enhanced
Block RAM (EBR) components found in every Lattice Semiconductor FPGA device. When implementing small
memories in the design, it is recommended to construct the memory from the resources in the PFU. The memory
utilizing resources in the PFU can also be generated by IPexpress.
Lattice Semiconductor FPGAs support many different memory types including synchronous dual-port RAM, syn-
chronous single-port RAM, synchronous FIFO and synchronous ROM. For more information on supported mem-
ory types per FPGA architecture, please consult the Lattice Semiconductor FPGA data sheets.
Preventing Logic Replication and Limited Fanout
Lattice Semiconductor FPGA device architectures are designed to handle high signal fanouts. When users make
use of clock resources, there will be no hindrance on fanout problems. However, synthesis tools tend to replicate
logic to reduce fanout during logic synthesis. For example, if the code implies Clock Enable and is synthesized with
speed constraints, the synthesis tool may replicate the Clock Enable logic. This kind of logic replication occupies
more resources in the devices and makes performance checking more difficult. It is recommended to control the
logic replication in synthesis process by using attributes for high fanout limit.
13-16
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