LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 210
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Table 9-14. PFU based Distributed Single port RAM Port Definitions
Users have an option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-
ures 8-35 and 8-36 show the internal timing waveforms for the Distributed Single Port RAM (Distributed_SPRAM)
with these options.
Figure 9-53. PFU Based Distributed Single Port RAM Timing Waveform - Without Output Registers
ClockEn
Address
Clock
Data
Clock
ClockEn
Reset
WE
Address
Data
Q
WE
Q
Generated Module
Port Name in
t
t
SUWREN_PFU
SUADDR_PFU
t
SUDATA_PFU
Data_0
Add_0
Invalid Data
CK
-
-
WRE
AD[3:0]
DI[1:0]
DO[1:0]
Port Name in the EBR
t
t
HADDR_PFU
HDATA_PFU
Block Primitive
Data_1
Add_1
t
HWREN_PFU
t
CORAM_PFU
9-45
Clock
Clock Enable
Reset
Write Enable
Address
Data In
Data Out
Add_0
Description
LatticeECP/EC and LatticeXP Devices
Data_0
Add_1
Data_1
Rising Clock Edge
Active High
Active High
Active High
—
—
—
Memory Usage Guide
Active State
Add_2
Data_2
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