LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 326
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LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Lattice ispTRACY Usage Guide
Figure 14-10. ispLA Project Setup Window - Event Pattern Setup
The Event Pattern window configures the patterns for EV0 and EV1. Pattern 0 corresponds to EV0 and Pattern 1
corresponds to EV1. The sample types for trigger signals depends on whether the signal is edge or level sensitive.
If the signal is level sensitive, in the middle pattern window, only logic 0 (0) ,logic (1) or don't care (X) are available.
For edge sensitive signals, the options are logic 0 (0), logic 1 (1), rising (R), falling (F), both/either edge (B) or don't
care (X). In this window, changes to the pattern are made in the center section (Pattern 1 or Pattern 0) and the
changes are reflected in the right section.
To begin sampling , click on the green run button. Sampling will complete when the trigger conditions are met. The
data will be uploaded through the JTAG cable and results displayed I the Signal Analysis window. Figure 14-11
shows the Signal Analysis window after a data capture cycle.
Figure 14-11. ispLA Signal Analysis Window
14-8
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