ATF1502ASL-25JU44 Atmel, ATF1502ASL-25JU44 Datasheet - Page 15
![IC CPLD EE LP 25NS 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATF1502ASL-25JU44
Manufacturer Part Number
ATF1502ASL-25JU44
Description
IC CPLD EE LP 25NS 44-PLCC
Manufacturer
Atmel
Series
ATF1502AS(L)r
Datasheet
1.ATF1502ASL-25JU44.pdf
(26 pages)
Specifications of ATF1502ASL-25JU44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
25.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
4.75 V ~ 5.25 V
Memory Type
EEPROM
Family Name
ATF1502ASL
# Macrocells
32
Number Of Usable Gates
750
Frequency (max)
60MHz
Propagation Delay Time
25ns
Number Of Logic Blocks/elements
2
# I/os (max)
32
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Number Of Product Terms Per Macro
40
Maximum Operating Frequency
60 MHz
Delay Time
25 ns
Number Of Programmable I/os
32
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
AC Characteristics
0995K–PLD–6/05
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
t
t
t
t
t
t
t
t
t
t
t
PD1
PD2
SU
H
FSU
FH
COP
CH
CL
ASU
AH
ACOP
ACH
ACL
CNT
CNT
ACNT
ACNT
MAX
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
ZX1
ZX2
Parameter
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered
Feedback
Global Clock Setup Time
Global Clock Hold Time
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
Logic Control Delay
Internal Output Enable Delay
Output Buffer and Pad Delay
(Slow slew rate = OFF;
V
Output Buffer Enable Delay
(Slow slew rate = OFF;
V
Output Buffer Enable Delay
(Slow slew rate = OFF;
V
CC
CCIO
CCIO
= 5V; C
= 5.0V; C
= 3.3V; C
L
= 35 pF)
L
L
= 35 pF)
= 35 pF)
(1)
166.7
Min
125
125
0.5
6
0
3
3
3
3
2
3
3
-7
Max
7.5
4.5
7.5
0.5
0.5
0.8
4.0
4.5
7
8
8
4
3
3
2
2
1
Min
100
100
125
0.5
7
0
3
4
4
3
3
4
4
-10
Max
0.5
0.5
0.8
1.5
5.0
5.5
10
10
10
10
9
5
1
5
5
5
2
76.9
76.9
Min
100
11
3
3
0
3
1
5
5
4
4
6
6
-15
Max
ATF1502AS(L)
15
12
15
13
13
8
2
2
2
8
1
6
6
3
4
7
7
Min
20
10
10
50
50
60
0
5
2
7
7
5
6
-25
Max
25
25
13
25
22
22
12
10
10
2
2
2
2
8
8
4
6
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15