ATF1502ASL-25JU44 Atmel, ATF1502ASL-25JU44 Datasheet - Page 8

• Manufacturer Part Number: ATF1502ASL-25JU44
• Description: IC CPLD EE LP 25NS 44-PLCC
• Manufacturer: Atmel
• Series: ATF1502AS(L)r

Specifications of ATF1502ASL-25JU44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 25.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 4.75 V ~ 5.25 V
• Memory Type: EEPROM
• Family Name: ATF1502ASL
• # Macrocells: 32
• Number Of Usable Gates: 750
• Frequency (max): 60MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 32
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 60 MHz
• Delay Time: 25 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant

ISP
Programming
Protection
JTAG-BST/ISP
Overview
8
ATF1502AS(L)
Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the
PC. ISP is performed by using either a download cable, a comparable board tester or a simple
microprocessor interface.
When using the ISP hardware or software to program the ATF1502AS devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for burned logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities.
ATF1502AS devices can also be programmed using standard third-party programmers. With a
third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional
I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
The ATF1502AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition, the pin-keeper option preserves the
previous state of the input and I/O PMS during programming.
All ATF1502AS devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
Note:
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1502AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and
I/O pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The
ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is
a u t o m a t i c a l l y r e s e t a t p o w e r - u p . T h e f i v e J T A G m o d e s s u p p o r t e d i n c l u d e :
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can
be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows
ATF1502AS programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502AS has the option of using four JTAG-standard I/O pins for boundary-scan test-
ing (BST) and in-system programming (ISP) purposes. The ATF1502AS is programmable
through the four JTAG pins using the IEEE standard JTAG programming protocol established
by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for
in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is
not needed, then the four JTAG control pins are available as I/O pins.
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
0995K–PLD–6/05