EPM570F100C4N Altera, EPM570F100C4N Datasheet - Page 19

• Manufacturer Part Number: EPM570F100C4N
• Description: IC MAX II CPLD 570 LE 100-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570F100C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 76
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 2.3148GHz
• Propagation Delay Time: 7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 76
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: FBGA
• No. Of I/o's: 76
• Propagation Delay: 7ns
• Global Clock Setup Time: 1.5ns
• Frequency: 247.5MHz
• Supply Voltage Range: 2.375V To 2.625V, 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1716

Chapter 2: MAX II Architecture
Logic Elements
Figure 2–9. Carry-Select Chain
© October 2008 Altera Corporation
LAB Carry-In
A1
B1
A2
B2
A3
B3
A4
B4
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A5
B5
The speed advantage of the carry-select chain is in the parallel precomputation of
carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE
is in the critical path. Only the propagation delays between LAB carry-in generation
(LE 5 and LE 10) are now part of the critical path. This feature allows the MAX II
architecture to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
Figure 2–9
portion of the LUT generates the sum of two bits using the input signals and the
appropriate carry-in bit; the sum is routed to the output of the LE. The register can be
bypassed for simple adders or used for accumulator functions. Another portion of the
LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for
the addition of given inputs. The carry-in signal for each chain, carry-in0 or
carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-
higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local,
row, or column interconnects.
LAB Carry-Out
0
0
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
1
1
Sum1
Sum2
Sum3
Sum4
Sum5
Sum6
Sum7
Sum8
Sum9
Sum10
shows the carry-select circuitry in an LAB for a 10-bit full adder. One
To top of adjacent LAB
LAB Carry-In
Carry-In0
Carry-In1
data1
data2
Carry-Out0
LUT
LUT
LUT
LUT
Carry-Out1
Sum
MAX II Device Handbook
2–11