EPM570F100C4N Altera, EPM570F100C4N Datasheet - Page 77

• Manufacturer Part Number: EPM570F100C4N
• Description: IC MAX II CPLD 570 LE 100-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570F100C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 76
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 2.3148GHz
• Propagation Delay Time: 7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 76
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: FBGA
• No. Of I/o's: 76
• Propagation Delay: 7ns
• Global Clock Setup Time: 1.5ns
• Frequency: 247.5MHz
• Supply Voltage Range: 2.375V To 2.625V, 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1716

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–23. EPM240 Global Clock External I/O Timing Parameters
Table 5–24. EPM570 Global Clock External I/O Timing Parameters
© August 2009 Altera Corporation
Symbol
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock
Symbol
t
t
t
t
t
t
t
t
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
input pin maximum frequency.
Table
Maximum
global clock
frequency for
16-bit
counter
Worst case pin-
to-pin delay
through 1 look-
up table (LUT)
Best case pin-
to-pin delay
through 1 LUT
Global clock
setup time
Global clock
hold time
Global clock to
output delay
Global clock
high time
Global clock
low time
Minimum
global clock
period for
16-bit counter
Parameter
Parameter
5–23:
Table 5–24
Condition
Condition
—
10 pF
10 pF
10 pF
—
—
—
—
—
shows the external I/O timing parameters for EPM570 devices.
Min
—
–3 Speed
Min
166
166
2.0
Grade
1.2
3.3
—
—
–3 Speed
0
Grade
304.0
Max
(1)
Max
5.4
3.7
4.5
—
—
—
—
—
MAX II / MAX IIG
MAX II / MAX IIG
Min
—
–4 Speed
Min
216
216
1.5
2.0
4.0
Grade
—
—
–4 Speed
0
Grade
247.5
Max
Max
7.0
4.8
5.8
—
—
—
—
—
Min
—
–5 Speed
(Part 2 of 2)
(Part 1 of 2)
Min
266
266
1.9
2.0
5.0
—
—
Grade
–5 Speed
0
Grade
201.1
Max
Max
8.7
5.9
7.1
—
—
—
—
—
Min
—
–6 Speed
Min
253
253
2.2
2.0
5.4
—
—
Grade
–6 Speed
0
Grade
184.1
Max
Max
9.5
5.7
6.7
—
—
—
—
—
Min
—
–7 Speed
MAX IIZ
Min
335
335
3.9
2.0
8.1
—
—
Grade
–7 Speed
0
MAX IIZ
Grade
123.5
Max
MAX II Device Handbook
Max
15.1
7.7
8.2
—
—
—
—
—
Min
—
–8 Speed
Min
339
339
4.4
2.0
8.4
Grade
—
—
–8 Speed
0
Grade
118.3 MHz
Max
Max
17.7
8.5
8.7
5–19
—
—
—
—
—
Unit
Unit
ns
ns
ns
ns
ns
ps
ps
ns