XA2C256-8TQG144Q Xilinx Inc, XA2C256-8TQG144Q Datasheet

IC CPLD 256MCELL 118 I/O 144TQFP

XA2C256-8TQG144Q

Manufacturer Part Number
XA2C256-8TQG144Q
Description
IC CPLD 256MCELL 118 I/O 144TQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheet

Specifications of XA2C256-8TQG144Q

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
118
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
XA2C256-8TQG144Q
Manufacturer:
XILINX
Quantity:
230
Part Number:
XA2C256-8TQG144Q
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XA2C256-8TQG144Q
Manufacturer:
XILINX
0
DS555 (v1.2) June 22, 2009
Features
© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS555 (v1.2) June 22, 2009
Product Specification
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
T
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
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Available in multiple package options
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Advanced system features
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A
= –40°C to +105°C with T
Optimized architecture for effective logic synthesis.
Refer to the CoolRunner™-II family data sheet for
architecture description.
Multi-voltage I/O operation — 1.5V to 3.3V
100-pin VQFP with 80 user I/O
144-pin TQFP with 118 user I/O
Pb-free only for all packages
Fastest in system programming
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IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Unsurpassed low power management
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Two separate I/O banks
RealDigital 100% CMOS product term generation
Flexible clocking modes
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Global signal options with macrocell control
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Advanced design security
PLA architecture
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Open-drain output option for Wired-OR and LED
drive
Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
1.8V ISP using IEEE 1532 (JTAG) interface
DataGATE enable (DGE) signal control
Optional DualEDGE triggered registers
Clock divider (divide by 2, 4, 6, 8, 10, 12, 14, 16)
CoolCLOCK
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
Superior pinout retention
100% product term routability across function
block
R
J
Maximum = +125°C
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www.xilinx.com
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XA2C256 CoolRunner-II
Automotive CPLD
Description
The CoolRunner-II Automotive 256-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved.
This device consists of sixteen Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as “direct input” registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
Product Specification
-
WARNING: Programming temperature range of
T
A
= 0°C to +70°C.
Hot pluggable
1

Related parts for XA2C256-8TQG144Q

XA2C256-8TQG144Q Summary of contents

Page 1

... Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS555 (v1.2) June 22, 2009 Product Specification 0 XA2C256 CoolRunner-II Automotive CPLD Product Specification 0 0 ...

Page 2

... LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II Automotive CPLDs are also Table 1). This 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XA2C256 IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 (1) LVCMOS15 requires Schmitt-trigger inputs ...

Page 3

... I I/O High-Z leakage IH Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block) tested at V DS555 (v1.2) June 22, 2009 Product Specification XA2C256 CoolRunner-II Automotive CPLD Description Device Package User Parameter Industrial T = –40°C to +85°C A Q-Grade T = –40°C to +105°C ...

Page 4

... Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage, OH Industrial grade High level output voltage, Q-grade DS555 (v1.2) June 22, 2009 Product Specification XA2C256 CoolRunner-II Automotive CPLD Test Conditions - - - I = –8 mA CCIO CCIO I = –0.1 mA ...

Page 5

... SUD T Setup time (single p-term) SU1 T Setup time (OR array) SU2 T Direct input register hold time HD T P-term hold time H T Clock to output CO DS555 (v1.2) June 22, 2009 Product Specification XA2C256 CoolRunner-II Automotive CPLD Test Conditions mA 1.7V OL CCIO I = 0.1 mA 1.7V OL CCIO mA 1.7V OL CCIO ...

Page 6

... F (1 the maximum external frequency using one p-term while F EXT1 SU1 CO 4. Typical configuration current during T DS555 (v1.2) June 22, 2009 Product Specification Parameter is approximately 7.7 mA. CONFIG www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD -7 -8 Min. Max. Min. Max. - 300 - 300 - 152 - 139 - 141 ...

Page 7

... Output slew rate adder SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder HYS18 T Output adder OUT18 T Output slew rate adder SLEW DS555 (v1.2) June 22, 2009 Product Specification XA2C256 CoolRunner-II Automotive CPLD -7 (2) Min. Max. - 2.6 - 3.9 - 2 ...

Page 8

... AC Test Circuit o C Device Under Test Output Type LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 C 1.5 nsec maximum rise/fall times on inputs DS092_02_092302 PD www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD -7 -8 Max. Min. Max. 0.7 - 0.7 3.0 - 3.0 1.0 - 1.0 4.0 - 4.0 0.7 - 0.7 3 ...

Page 9

... DS555 (v1.2) June 22, 2009 Product Specification 3.3V 2.5V 1.8V 1.5V .5 1.0 1.5 2.0 VO (Output Volts) Figure 4: Typical I/V Curve for XA2C256 www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD Iol 2.5 3.0 3.5 XC256_VoIo_all_020703 9 ...

Page 10

... DS555 (v1.2) June 22, 2009 Product Specification Pin Descriptions (Continued) Function Block TQG144 I/O Bank 143 2 3 142 140 139 2 3 138 2 3 137 www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD Macro- cell VQG100 TQG144 1 - 136 2 - 135 3 - 134 133 132 131 I/O Bank ...

Page 11

... R Pin Descriptions (Continued) Macro- Function Block cell VQG100 5(GCK1 5(GCK0 (CDRST 6(GCK2 6(DGE DS555 (v1.2) June 22, 2009 Product Specification Pin Descriptions (Continued) TQG144 I/O Bank Function Block - www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD Macro- cell VQG100 TQG144 I/O Bank ...

Page 12

... XA2C256 CoolRunner-II Automotive CPLD Macro- cell VQG100 TQG144 120 6 - 121 124 12 86 125 13 87 126 14 89 128 15 - 129 16 - 130 100 3 ...

Page 13

... Function Block Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. 2. GTS, GSR and GCK pins can be used for general purpose I/O. www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD Macro- cell VQG100 TQG144 I/O Bank ...

Page 14

... CCIO2 Ground No connects Total user I/O Ordering Information Pin/Ball Part Number Spacing XA2C256-7VQG100I 0.5mm XA2C256-8VQG100Q 0.5mm XA2C256-7TQG144I 0.5mm XA2C256-8TQG144Q 0.5mm Notes Industrial (T = –40°C to +85°C Automotive ( Pb- Free Example: XA2C256 Device Speed Grade Package Type Pb -Free Number of Pins Temperature Range DS555 (v1.2) June 22, 2009 ...

Page 15

... Device Type Package Speed Operating Range DS555 (v1.2) June 22, 2009 Product Specification R XA2Cxxx TQG144 7 I Part Marking for all non chip scale packages Figure 5: Sample Package with Part Marking www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD This line not related to device part number 15 ...

Page 16

... I/O 20 VCCIO1 21 GND 22 I/O (2) 23 I/O (2) 24 I/O (4) 25 GND DS555 (v1.2) June 22, 2009 Product Specification VQG100 Top View Figure 6: VQG100 Very Thin Quad Flat Pack www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD GND 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 GND 69 I/O 68 I/O 67 I/O ...

Page 17

... Do not drive I/O pins without V 4. Sink current when driving LEDs. Because all Xilinx CPLDs have N-channel pull-down transistors on outputs required that an LED anode is sourced through a resistor externally to V will give the brightest solution. www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD GND 108 I/O 107 I/O 106 ...

Page 18

... CPLD to reduce switching noise. 10. Terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. These and other application notes can be accessed at: CoolRunner-II Documentation Package specifications can be accessed at: Device Packages www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD CCI for the applications in which any CCIO (internal 18 ...

Page 19

... INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS555 (v1.2) June 22, 2009 Product Specification Revision specification for 3.3V, 2.5V and 1.8V LVCMOS. IH Figure 7. THE XILINX LIMITED WARRANTY www.xilinx.com XA2C256 CoolRunner-II Automotive CPLD WHICH CAN BE VIEWED AT 19 ...

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