XA2C256-8TQG144Q Xilinx Inc, XA2C256-8TQG144Q Datasheet - Page 17

• Manufacturer Part Number: XA2C256-8TQG144Q
• Description: IC CPLD 256MCELL 118 I/O 144TQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XA2C256-8TQG144Q

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 6000
• Number Of I /o: 118
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Features: JTAG
• Voltage: 1.8V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

CoolRunner-II Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applica-
tions:
1. Use a monotonic, fast ramp power supply to power up
2. Do not float I/O pins during device operation. Floating
DS555 (v1.2) June 22, 2009
Product Specification
CoolRunner-II. A V
required.
I/O pins can increase I
1–2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
R
V
CCIO1
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
V
AUX
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(1)
(1)
(1)
(1)
(2)
(2)
(4)
CC
ramp time of less than 1 ms is
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
as input buffers will draw
Figure 7: TQG144 Thin Quad Flat Pack
www.xilinx.com
Top View
TQG144
3. Do not drive I/O pins without V
4. Sink current when driving LEDs. Because all Xilinx
I/O pins should be appropriately terminated with bus-
hold or pull-up. Unused I/Os can also be configured as
C
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to V
will give the brightest solution.
GND
(programmable GND).
XA2C256 CoolRunner-II Automotive CPLD
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
CC
CC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
V
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
/V
CCIO1
CC
CCIO1
. Consequently, this
CCIO
powered.
17