ADSP-21261SKSTZ150 Analog Devices Inc, ADSP-21261SKSTZ150 Datasheet - Page 26

• Manufacturer Part Number: ADSP-21261SKSTZ150
• Description: IC DSP 32BIT 150MHZ 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKSTZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 150MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic: RoHS Compliant
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 150 MHz
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21261
Table 20. 16-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
D = (data cycle duration) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
CCLK
(if a hold cycle is specified, else H = 0)
Address/Data15–0 Setup Before RD high
Address/Data15–0 Hold After RD high
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data15–0 Setup Before ALE Deasserted
Address/Data15–0 Hold After ALE Deaserted
ALE Deasserted
RD Pulse Width
AD15–0
ALE
WR
RD
CCLK
1
to Address/Data15–0 in High Z
VALID ADDRESS
t
ADAS
t
ALEW
Figure 18. 16-Bit Memory Read Cycle
Rev. 0 | Page 26 of 44 | March 2006
t
ADAH
t
t
ALERW
ALEHZ
1
1
t
RW
t
VALID DATA
DRS
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
CCLK
CCLK
CCLK
CCLK
CCLK
t
DRH
– 2
– 0.5
– 2.0
– 0.8
– 0.8
Max
0.5t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns