ADSP-21261SKSTZ150 Analog Devices Inc, ADSP-21261SKSTZ150 Datasheet - Page 31

• Manufacturer Part Number: ADSP-21261SKSTZ150
• Description: IC DSP 32BIT 150MHZ 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKSTZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 150MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic: RoHS Compliant
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 150 MHz
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SCLK)
(SCLK)
(FS)
(FS)
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
t
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DRIVE EDGE
DRIVE EDGE
HOFSI
HDTI
HOFSI
DATA TRANSMIT—INTERNAL CLOCK
DATA RECEIVE—INTERNAL CLOCK
SCLK (INT)
DAI_P20–1
SCLK (EXT)
DAI_P20–1
DAI_P20–1
DAI_P20–1
t
DFSI
t
DFSI
t
t
SCLKIW
SCLKIW
t
DDTI
DRIVE EDGE
DRIVE EDGE
t
t
t
SDRI
SFSI
SFSI
SAMPLE EDGE
SAMPLE EDGE
Rev. 0 | Page 31 of 44 | March 2006
t
DDTIN
Figure 22. Serial Ports
t
DDTEN
t
t
t
HFSI
HFSI
HDRI
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SCLK)
(SCLK)
(FS)
(FS)
t
DRIVE EDGE
DRIVE EDGE
t
HOFSE
HDTE
t
HOFSE
SCLK
DATA TRANSMIT—EXTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
t
t
DFSE
DFSE
t
DDTTE
t
t
SCLKW
SCLKW
DRIVE EDGE
t
DDTE
t
t
t
SFSE
SDRE
SFSE
SAMPLE EDGE
SAMPLE EDGE
ADSP-21261
t
HFSE
t
t
HDRE
HFSE