DSPB56371AF150 Freescale Semiconductor, DSPB56371AF150 Datasheet - Page 2

• Manufacturer Part Number: DSPB56371AF150
• Description: IC DSP 24BIT 150MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56371AF150

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 264kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 150 MIPs
• Maximum Clock Frequency: 150 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 264 KB
• Operating Supply Voltage: 1.25 V, 3.3 V
• Maximum Operating Temperature: + 115 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DSP56371 Overview
the DSP56300 family of programmable CMOS DSPs. The DSP56371 is targeted to applications that
require digital audio compression/decompression, sound field processing, acoustic equalization and other
digital audio algorithms. Changes in core functionality specific to the DSP56371 are also described in this
manual. See
2.2
The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that
provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code
compatibility with it.
2
2
PINIT/NMI
5
Interface
RESET
EXTAL
DSP56300 Core Description
SHI
erator
Clock
Gen-
Figure 1.
Bootstrap
Internal
Six Channel
Switch
Generation
DMA Unit
ROM
Data
Bus
DAX
Address
2
Unit
Triple
Timer
PLL
12
for the block diagram of the DSP56371.
Interface Interface
ESAI
Controller
Program
Interrupt
12
ESAI_1
Figure 1. DSP56371 Block Diagram
Expansion Area
11
Peripheral
DSP56371 Data Sheet, Rev. 4.1
GPIO
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Controller
Program
Decode
EFCOP
Generator
Program
Address
Program
64K × 24
4K × 24
RAM
ROM
GDB
DDB
YDB
XDB
PDB
DSP56300
24-Bit
Core
DAB
24 × 24 + 56 → 56-bit MAC
XAB
Two 56-bit Accumulators
YAB
PAB
Memory Expansion Area
56-bit Barrel Shifter
36K × 24
32K × 24
Data ALU
X Data
RAM
ROM
32K × 24
48K × 24
Y Data
ROM
RAM
Freescale Semiconductor
OnCE™
Power
Mgmt.
JTAG
4