MSC8113TMP4800V Freescale Semiconductor, MSC8113TMP4800V Datasheet - Page 19

• Manufacturer Part Number: MSC8113TMP4800V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP4800V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 11 summarizes the reset actions that occur as a result of the different reset sources.
2.5.4.1
Asserting
V
Freescale Semiconductor
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Software
watchdog reset
Bus monitor reset
Host reset
command through
the TAP
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
SPLL state reset
System reset configuration write through
the DSI
System reset configuration write though
the system bus
HRESET driven
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
SRESET driven
SC140 extended cores reset
MQBS reset
DD
and
Reset Action/Reset Source
Name
V
PORESET
DDH
are both at their nominal levels.
Power-On Reset (PORESET) Pin
Input/ Output
Input/ Output
initiates the power-on reset flow.
Direction
Internal
Internal
Internal
Input
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Table 11. Reset Actions for Each Reset Source
Initiates the power-on reset flow that resets the MSC8113 and configures various attributes of the
MSC8113. On PORESET, the entire MSC8113 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8113. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8113 Reference Manual.
Initiates the soft reset flow. The MSC8113 detects an external assertion of SRESET only if it occurs
while the MSC8113 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
When the MSC8113 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC8113 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
External only
(PORESET)
Power-On
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 10. Reset Sources
PORESET
(Software Watchdog or
Hard Reset (HRESET)
External or Internal
Bus Monitor)
must be asserted externally for at least 16
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Description
External
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Soft Reset (SRESET)
Electrical Characteristics
EXTEST, CLAMP, or
Depends on command
JTAG Command:
CLKIN
HIGHZ
Yes
Yes
Yes
No
No
No
No
No
No
cycles after
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