MSC8113TMP4800V Freescale Semiconductor, MSC8113TMP4800V Datasheet - Page 40

• Manufacturer Part Number: MSC8113TMP4800V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP4800V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Design Considerations
Note:
Note:
Note:
3.4
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 133 MHz operation, you may have to use 133 or 166 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8113 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
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If there is an external bus master (BCR[EBM] = 1):
—
—
In single-master mode,
modes, they must be pulled up.
The MSC8113 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is
disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).
If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the
available clock modes.
In the
— Connect the oscillator output through a buffer to
— Connect
— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
See the Clock chapter in the MSC8113 Reference Manual for details.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set,
should be pulled up.
The following signals:
used to configure the MSC8113 and are sampled on the deassertion of the
be tied to
When they are used,
be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected,
externally to any signal line.
For details on configuration, see the MSC8113 User’s Guide and MSC8113 Reference Manual. For additional
information, refer to the MSC8113 Design Checklist (ANxxxx).
BR
EXT_BR[2–3]
functionality.
between the clock buffer to the MSC8113 and the SDRAM is equal (that is, has a skew less than 100 ps).
External SDRAM Selection
CLKIN
,
BG
GND
,
DBG
the CLKIN
synchronization mode, use the following connections:
or
, and
,
V
EXT_BG[2–3]
DDH
INT_OUT
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
TS
SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3]
ABB
or through a pull-down or a pull-up resistor until the deassertion of the
buffer output to the slave device (for example, SDRAM) making sure that the delay path
must be pulled up.
and
(if SIUMCR[INTODC] is cleared),
DBB
, and
can be selected as
EXT_DBG[2–3]
CLKIN
must be pulled up if multiplexed to the system bus
IRQ
.
inputs and be connected to the non-active value. In other
NMI_OUT
GPIO10
PPBS
PORESET
, and
can be disconnected. Otherwise, it
IRQxx
and
GPIO14
signal. Therefore, they should
,
RSTCONF
(if not full drive) signals must
Freescale Semiconductor
must not be connected
PORESET
and
BM[0–2]
signal.
are