MSC8113TMP4800V Freescale Semiconductor, MSC8113TMP4800V Datasheet - Page 38

• Manufacturer Part Number: MSC8113TMP4800V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP4800V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Design Considerations
3
The following sections discuss areas to consider when the MSC8113 device is designed into a system.
3.1
Use the following guidelines for start-up and power-down sequences:
Note:
External voltage applied to any input line must not exceed the I/O supply
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
After power-up,
3.2
When implementing a new design, use the guidelines described in the MSC8113 Design Checklist (AN3374 for optimal system
performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed
design information.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
38
Voltage Regulator
Power supply
(I
min
•
•
•
•
•
or
= 3 A)
Assert
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN
start toggling before the deassertion of
If possible, bring up
V
voltage levels down together. If that is not possible reverse the power-up sequence, with
then
This recommended power sequencing for the MSC8113 is different from the MSC8102.
For the core supply, use a voltage regulator rated at 1.1 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8113 device.
DDH
Hardware Design Considerations
Start-up Sequencing Recommendations
Power Supply Design Considerations
V
.
DD
V
PORESET
can be held low or allowed to toggle during the beginning of the power-up sequence. However,
V
DDH
/
DDH
V
+
-
CCSYN
1.1 V
should not exceed
must not exceed
.
and
V
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
DD
TRST
/
V
CCSYN
Note: Use at least three capacitors.
Each capacitor must be at least 150 μF.
before applying power and keep the signals driven low until the power reaches the
Figure 33. Core Power Supply Decoupling
V
V
DD
DD
and
/
Maximum IR drop
of 15 mV at 1 A
/
V
V
CCSYN
CCSYN
Bulk/Tantalum capacitors
V
with low ESR and ESL
PORESET
DDH
by more than 2.6 V.
together. If it is not possible, raise
until
V
and after both power supplies have reached nominal voltage levels.
DD
/
V
CCSYN
reaches its nominal voltage level. Similarly, bring both
V
DDH
by more than 0.8 V at any time, including during
L
max
= 2 cm
V
DD
/
V
CCSYN
High frequency capacitors
One 0.01 µF capacitor
for every 3 core supply
(very low ESR and ESL)
pads.
V
DDH
first and then bring up
Freescale Semiconductor
going down first and
CLKIN
MSC8113
must