MSC8113TMP4800V Freescale Semiconductor, MSC8113TMP4800V Datasheet - Page 22

• Manufacturer Part Number: MSC8113TMP4800V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP4800V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the
22
Notes:
No.
11a
11b
11c
11d
13
14
15a
15b
10
12
16
17
18
1
1
1.
2.
3.
Hold time for all signals after the 50% level of the REFCLK rising edge
ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising
edge
AACK set-up time before the 50% level of the REFCLK rising edge
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge
•
•
Data bus set-up time before REFCLK rising edge in Normal mode
•
•
Data bus set-up time before the 50% level of the REFCLK rising edge in ECC
and PARITY modes
•
•
DP set-up time before the 50% level of the REFCLK rising edge
•
•
TS and Address bus set-up time before the 50% level of the REFCLK rising edge
•
•
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the
REFCLK rising edge
•
•
PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge
IRQx setup time before the 50% level; of the REFCLK rising edge
IRQx minimum pulse width
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
Guaranteed by design.
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
3
Characteristic
Table 14. AC Timing for SIU Inputs
3
Ref = CLKIN at 1.1 V
and 100/133 MHz
6.0 + T
0.5
3.1
3.6
3.0
3.5
4.4
1.9
4.2
2.0
8.2
2.0
7.9
4.2
5.5
3.7
4.8
3.7
4.0
REFCLK
Freescale Semiconductor
REFCLK
rising edge.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns