ADSP-2186KSTZ-133 Analog Devices Inc, ADSP-2186KSTZ-133 Datasheet - Page 7

• Manufacturer Part Number: ADSP-2186KSTZ-133
• Description: IC DSP CONTROLLER 16BIT 100LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2186KSTZ-133

• Interface: Host Interface, Serial Port
• Clock Rate: 33.3MHz
• Non-volatile Memory: External
• On-chip Ram: 40kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 33.3MHz
• Mips: 33.3
• Device Input Clock Speed: 33.3MHz
• Ram Size: 40KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2186, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. The ADSP-2186 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
CONTROLLER
INTERFACE
1/2x CLOCK
1/2x CLOCK
SYSTEM
CRYSTAL
CRYSTAL
OR
SERIAL
DEVICE
SERIAL
DEVICE
DEVICE
DEVICE
SERIAL
SERIAL
OR
OR
16
FULL MEMORY MODE
HOST MEMORY MODE
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15–0
CLKIN
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
CLKIN
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
MODE C/PF2
MODE B/PF1
MODE A/PF0
IDMA PORT
SPORT1
SPORT0
SPORT1
SPORT0
ADSP-2186
ADSP-2186
ADDR13–0
DATA23–0
DATA23–8
PWDACK
PWDACK
ADDR0
IOMS
IOMS
BMS
PMS
DMS
CMS
BGH
PWD
BMS
DMS
CMS
PMS
BGH
PWD
BG
BR
BR
BG
14
1
16
24
D
A
23–16
A
A
13–0
D
D
D
10–0
13–0
15–8
23–0
23–8
DATA
DATA
DATA
A0–A21
CS
ADDR
CS
ADDR
(PERIPHERALS)
DM SEGMENTS
PM SEGMENTS
2048 LOCATIONS
OVERLAY
MEMORY
I/O SPACE
TWO 8K
TWO 8K
MEMORY
BYTE
Clock Signals
The ADSP-2186 can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information on this power-down feature,
refer to the ADSP-218x DSP Hardware Reference.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2186 uses an input clock with a frequency equal to
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2186 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used.
A clock output (CLKOUT) signal is generated by the proces-
sor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
Reset
The RESET signal initiates a master reset of the ADSP-2186.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, t
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
CLKIN
DSP
XTAL
RSP
.
CLKOUT
ADSP-2186
DD
is