EP2C8T144C7N Altera, EP2C8T144C7N Datasheet - Page 89
EP2C8T144C7N
Manufacturer Part Number
EP2C8T144C7N
Description
IC CYCLONE II FPGA 8K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8T144C7N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
85
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1667
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8T144C7N
Manufacturer:
Altera
Quantity:
135
Company:
Part Number:
EP2C8T144C7N
Manufacturer:
ATLERA
Quantity:
10
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Conclusion
Document
Revision History
Altera Corporation
February 2007
February 2007
v3.1
July 2005 v2.0
February 2005
v1.1
June 2004 v1.0
Table 4–1. Document Revision History
Document
Version
Date &
●
●
●
●
Updated technical content throughout.
Removed ESD section.
Added document to the Cyclone II Device Handbook.
Added document revision history.
Updated
section.
Updated
Added footnote to
If you cannot meet the maximum V
use an external component to hold nCONFIG low until the power supplies
have reached their minimum recommend operating levels. Otherwise,
the device may not properly configure and enter user mode.
Cyclone II devices are hot socketable and support all power-up and
power-down sequences with the one requirement that V
be powered up and down within 100 ms of each other to keep the I/O
pins from driving out. Cyclone II devices do not require any external
devices for hot socketing and power sequencing.
Table 4–1
“I/O Pins Remain Tri-Stated during Power-Up”
“Power-On Reset Circuitry”
Figure
Changes Made
shows the revision history for this document.
4–3.
section.
CC
Cyclone II Device Handbook, Volume 1
ramp time requirement, you must
Hot Socketing & Power-On Reset
●
●
●
Specified V
supplies must be GND
when "not powered".
Added clarification about
input-tristate behavior.
Added infomation on V
monotonic ramp.
Summary of Changes
CCIO
CCIO
and V
and V
CCINT
CCINT
CC
4–7
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