XC3S500E-4FGG320C Xilinx Inc, XC3S500E-4FGG320C Datasheet - Page 128

• Manufacturer Part Number: XC3S500E-4FGG320C
• Description: IC SPARTAN-3E FPGA 500K 320FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FGG320C

• Total Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Number Of I /o: 232
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 320-BGA
• No. Of Logic Blocks: 10476
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• No. Of Speed Grades: 4
• No. Of I/o's: 250
• Clock Management: DLL
• Package: 320FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1526

DC and Switching Characteristics
Table 87: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
128
Notes:
1.
2.
3.
4.
Setup Times
T
T
Hold Times
T
T
Symbol
PSDCM
PSFD
PHDCM
PHFD
The numbers in this table are tested using the methodology presented in
Table 77
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
and
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is used. No
Input Delay is programmed.
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition
at the Global Clock pin. The
DCM is not used. The Input
Delay is programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is used. No
Input Delay is programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not used.
The Input Delay is programmed.
Table
80.
Description
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE =
default software setting
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE =
default software setting
Conditions
(4)
(4)
www.xilinx.com
(2)
(2)
(3)
(3)
,
,
,
,
Table 95
DELAY_
VALUE=
IFD_
0
2
3
3
3
3
0
2
3
3
3
3
and are based on the operating conditions set forth in
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Table
Table
Device
91. If this is true of the data Input, subtract the
91. If this is true of the data Input, add the
DS312-3 (v3.8) August 26, 2009
–0.54
–0.31
–0.32
–0.77
–0.05
2.65
2.25
2.25
2.25
2.25
3.16
3.44
4.00
2.60
3.33
0.06
0.07
0.07
0.06
0.13
Min
-5
Speed Grade
Product Specification
–0.52
–0.24
–0.32
–0.77
–0.03
2.98
2.59
2.59
2.58
2.59
3.58
3.91
4.73
3.31
3.77
0.14
0.14
0.15
0.14
0.16
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R