EPF8452AQC160-4 Altera, EPF8452AQC160-4 Datasheet - Page 23

IC FLEX 8000A FPGA 4K 160-PQFP

EPF8452AQC160-4

Manufacturer Part Number
EPF8452AQC160-4
Description
IC FLEX 8000A FPGA 4K 160-PQFP
Manufacturer
Altera
Series
FLEX 8000r
Datasheet

Specifications of EPF8452AQC160-4

Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
120
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-2259

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Output
Configuration
Control Signal
Table 5. Row Sources of FLEX 8000 Peripheral Control Signals
Peripheral
CLK0
CLK1/OE1
CLR0
CLR1/OE0
OE2
OE3
OE4
OE5
OE6
OE7
OE8
OE9
f
EPF8282A
EPF8282AV
Row A
Row B
Row A
Row B
Row A
Row B
Table 5
device by row.
This section discusses slew-rate control and MultiVolt I/O interface
operation for FLEX 8000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slow slew rate
reduces system noise by slowing signal transitions, adding a maximum
delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of
a signal. The fast slew rate should be used for speed-critical outputs in
systems that are adequately protected against noise. Designers can specify
the slew rate on a pin-by-pin basis during design entry or assign a default
slew rate to all pins on a global basis.
For more information on high-speed system design, go to
Note 75 (High-Speed Board
EPF8452A
Row A
Row B
Row A
Row B
Row A
Row B
lists the source of the peripheral control signal for each FLEX 8000
FLEX 8000 Programmable Logic Device Family Data Sheet
EPF8636A
Row C
Row C
Row A
Row B
Row A
Row B
Designs).
EPF8820A
Row A
Row C
Row B
Row D
Row A
Row B
EPF81188A
Row E
Row B
Row C
Row D
Row A
Row F
Application
EPF81500A
Row C
Row C
Row D
Row D
Row E
Row B
Row F
Row A
Row A
Row B
Row E
Row F
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