EPF8452AQC160-4 Altera, EPF8452AQC160-4 Datasheet - Page 8

• Manufacturer Part Number: EPF8452AQC160-4
• Description: IC FLEX 8000A FPGA 4K 160-PQFP
• Manufacturer: Altera
• Series: FLEX 8000r

Specifications of EPF8452AQC160-4

• Number Of Logic Elements/cells: 336
• Number Of Labs/clbs: 42
• Number Of I /o: 120
• Number Of Gates: 4000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 544-2259

FLEX 8000 Programmable Logic Device Family Data Sheet
8
The FLEX 8000 architecture provides two dedicated high-speed data
paths—carry chains and cascade chains—that connect adjacent LEs
without using local interconnect paths. The carry chain supports high-
speed counters and adders; the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in an LAB and all LABs in the same row. Heavy use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of carry and
cascade chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (less than 1 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit moves
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 8000 architecture to implement high-speed counters and adders of
arbitrary width. The MAX+PLUS II Compiler can create carry chains
automatically during design processing; designers can also insert carry
chain logic manually during design entry.
Figure 4
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register is typically bypassed for simple adders, but
can be used for an accumulator function. Another portion of the LUT and
the carry chain logic generate the carry-out signal, which is routed directly
to the carry-in signal of the next-higher-order bit. The final carry-out
signal is routed to another LE, where it can be used as a general-purpose
signal. In addition to mathematical functions, carry chain logic supports
very fast counters and comparators.
shows how an n-bit full adder can be implemented in n + 1 LEs
Altera Corporation