EP2S15F484C5N Altera, EP2S15F484C5N Datasheet - Page 214
EP2S15F484C5N
Manufacturer Part Number
EP2S15F484C5N
Description
IC STRATIX II FPGA 15K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S15F484C5N
Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
15600
# I/os (max)
342
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
15600
Ram Bits
419328
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
342
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1876
EP2S15F484C5N
EP2S15F484C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S15F484C5N
Manufacturer:
ALTERA30
Quantity:
206
Part Number:
EP2S15F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Duty Cycle Distortion
Figure 5–8. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
5–78
Stratix II Device Handbook, Volume 1
clk
INPUT
VCC
Figure 5–7. Duty Cycle Distortion
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions
present on the input clock signal or caused by the clock input buffer or
different input I/O standard does not transfer to the output signal.
IOE
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
5–7, is clock-period independent. DCD can also be expressed as a
NOT
inst1
CLKH = T/2
Falling Edge A
DFF
inst
Ideal Falling Edge
Clock Period (T)
D
CLRN
PRN
D1
Q
D2
(Figure
Falling Edge B
CLKL = T/2
5–8). Therefore, any DCD
OUTPUT
Altera Corporation
output
April 2011
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