EP2S15F484C5N Altera, EP2S15F484C5N Datasheet - Page 86

• Manufacturer Part Number: EP2S15F484C5N
• Description: IC STRATIX II FPGA 15K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F484C5N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 15600
• # I/os (max): 342
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15600
• Ram Bits: 419328
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Family Type: Stratix II
• No. Of I/o's: 342
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1876; EP2S15F484C5N

I/O Structure
Figure 2–52. Stratix II IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
(4)
2–78
Stratix II Device Handbook, Volume 1
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
Figure
ioe_clk[7..0]
DQS Local
2–52:
Bus (2)
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used in the IOE
for DDR input acquisition. The latch holds the data that is present during
the clock high times. This allows both bits of data to be synchronous with
the same clock edge (either rising or falling).
configured for DDR input.
diagram.
Input Register
Input Register
D
CLRN/PRN
ENA
CLRN/PRN
D
ENA
Input RegisterDelay
I
nput Pin to
Q
Q
Figure 2–53
Notes
(1), (2),
D
ENA
CLRN/PRN
To DQS Logic
Latch
Block (3)
shows the DDR input timing
Q
(3)
Figure 2–52
VCCIO
VCCIO
PCI Clamp (4)
Altera Corporation
shows an IOE
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
May 2007