EP2S15F484C5N Altera, EP2S15F484C5N Datasheet - Page 219

• Manufacturer Part Number: EP2S15F484C5N
• Description: IC STRATIX II FPGA 15K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F484C5N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 15600
• # I/os (max): 342
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15600
• Ram Bits: 419328
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Family Type: Stratix II
• No. Of I/o's: 342
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1876; EP2S15F484C5N

Altera Corporation
April 2011
Notes to
(1)
(2)
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS/ HyperTransport
technology
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
DDIO Column Output I/O
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Row DDIO Output I/O
Table 5–83
The DCD specification is based on a no logic array noise condition.
Standard
Standard
Table
Notes
5–83:
assumes the input clock has zero DCD.
(1),
(2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
3.3/2.5 V
Notes
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
3.3/2.5 V
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
440
390
375
325
430
355
350
335
330
330
180
260
210
195
TTL/CMOS
(1),
TTL/CMOS
(2)
1.8/1.5 V
Clock Port (No PLL in the Clock Path)
1.8/1.5 V
495
450
430
385
490
410
405
390
385
390
180
Port (No PLL in the Clock Path)
380
330
315
SSTL-2
2.5 V
170
120
105
160
180
90
85
80
65
60
60
SSTL-2
2.5 V
145
100
85
SSTL/HSTL
1.8/1.5 V
160
110
100
155
180
SSTL/HSTL
95
75
70
65
70
70
Stratix II Device Handbook, Volume 1
1.8/1.5 V
145
100
85
DC & Switching Characteristics
HyperTransport
Technology
LVDS/
3.3 V
105
135
100
105
110
105
180
75
90
85
90
1.2-V
HSTL
1.2 V
145
100
85
Unit
ps
ps
ps
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
5–83