EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 208

• Manufacturer Part Number: EP2SGX60EF1152I4
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2186

Operating Conditions
4–38
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Serial RapidIO
SDI
BASIC Single
Width
BASIC Double
Width
Table 4–21. PCS Latency (Part 2 of 2)
Functional Mode
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver
interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation FIFO
latency. For more details, refer to the CPRI Mode section in the
chapter in volume 2 of the Stratix II GX Device Handbook.
Table
4–21:
10-bit channel
20-bit channel
Configuration
channel width
channel width
channel width
channel width
16-bit/20-bit
16-bit/20-bit
32-bit/40-bit
3.125 Gbps
1.25 Gbps,
8-bit/10-bit
Loopback/
2.5 Gbps,
HD, 3G
Parallel
width
width
BIST
HD
TX PIPE
Note (1)
-
-
-
-
-
-
-
-
Phase
Comp
FIFO
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
TX
Transmitter PCS Latency
Serializer
Byte
Stratix II GX Transceiver Architecture Overview
1
1
1
1
1
1
1
1
TX State
Machine
-
-
-
-
-
-
-
-
Encoder
8B/10B
0.5
0.5
0.5
0.5
1
1
1
1
Altera Corporation
Sum
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
(2)
June 2009