EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 311

IC STRATIX II GX 60K 1152-FBGA

EP2SGX60EF1152I4

Manufacturer Part Number
EP2SGX60EF1152I4
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX60EF1152I4

Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2186

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX60EF1152I4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX60EF1152I4
Manufacturer:
ALTERA
0
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
534
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
300
Part Number:
EP2SGX60EF1152I4N
0
April 2006, v3.0
February 2006,
v2.1
December 2005,
v2.0
October 2005
v1.1
October 2005
v1.0
Table 4–118. Document Revision History (Part 5 of 5)
Document
Date and
Version
Updated timing numbers.
Added chapter to the Stratix II GX Device
Handbook.
Updated Table 6–3.
Updated Table 6–5.
Updated Table 6–7.
Added Table 6–42.
Updated “Internal Timing Parameters” section
(Tables 6–43 through 6–48).
Updated “Stratix II GX Clock Timing
Parameters” section (Tables 6–49 through
6–65).
Updated “IOE Programmable Delay” section
(Tables 6–67 and 6–68)
Updated “I/O Delays” section (Tables 6–71
through 6–74.
Updated “Maximum Input & Output Clock Toggle
Rate” section. Replaced tables 6-73 and 6-74
with Tables 6–75 through 6–83. Input and output
clock rates for row, column, and dedicated clock
pins are now in separate tables.
Updated Tables 6–4 and 6–5.
Updated Tables 6–49 through 6–65 (removed
column designations for industrial/commercial
and removed industrial numbers).
Updated Table 6–7.
Updated Table 6–38.
Updated 3.3-V PCML information and notes to
Tables 6–73 through 6–76.
Minor textual changes throughout the
document.
Changes Made
Summary of Changes

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