EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 191
![IC STRATIX FPGA 20K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S20F672I7
Manufacturer Part Number
EP1S20F672I7
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F672I7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
Quantity:
212
- Current page: 191 of 276
- Download datasheet (4Mb)
Altera Corporation
January 2006
Notes to
(1)
(2)
(3)
(4)
(5)
TriMatrix
memory
M-RAM
block
DSP block
Larger
Designs
Table 4–36. Stratix Performance (Part 2 of 2)
These design performance numbers were obtained using the Quartus II software.
Numbers not listed will be included in a future version of the data sheet.
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses registered multiplier input, pipeline, and output stages within the DSP
block.
Table
Applications
True dual-port
RAM 16K × 36 bit
Single port
RAM 32K × 18 bit
Simple dual-port
RAM 32K × 18 bit
True dual-port
RAM 32K × 18 bit
Single port
RAM 64K × 9 bit
Simple dual-port
RAM 64K × 9 bit
True dual-port
RAM 64K × 9 bit
9 × 9-bit multiplier
18 × 18-bit multiplier
(4)
36 × 36-bit multiplier
(4)
36 × 36-bit multiplier
(5)
18-bit, 4-tap FIR filter
8-bit, 16-tap parallel
FIR filter
8-bit, 1,024-point FFT
function
4–36:
(3)
LEs
870
58
0
0
0
0
0
0
0
0
0
0
0
0
Resources Used
TriMatrix
Memory
Blocks
1
1
1
1
1
1
1
0
0
0
0
0
0
5
Notes
(1),
Blocks
DSP
0
0
0
0
0
0
0
1
1
1
1
1
4
1
(2)
269.83
275.86
275.86
275.86
287.85
287.85
287.85
278.78
148.25
278.78
278.78
141.26
261.09
Speed
Grade
335.0
-5
Stratix Device Handbook, Volume 1
237.69
244.55
244.55
244.55
253.29
253.29
253.29
293.94
237.41
134.71
237.41
237.41
133.49
235.51
Speed
Grade
-6
DC & Switching Characteristics
Performance
206.82
212.76
212.76
212.76
220.36
220.36
220.36
255.68
206.52
117.16
206.52
206.52
114.88
205.21
Speed
Grade
-7
175.74
180.83
180.83
180.83
187.26
187.26
187.26
217.24
175.50
175.50
100.28
175.22
Speed
Grade
99.59
175.5
-8
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4–21
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