EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 92

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

PLLs & Clock Networks
2–78
Stratix Device Handbook, Volume 1
Figure 2–45. EP1S30 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Notes to
(1)
(2)
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, four regional clock lines, and two fast
regional clock lines. Multiplexers are used with these clocks to form eight
bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select two of the eight row
clocks to feed the LE registers within the LAB. See
This is a set of two multiplexers.
In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
(1), (2)
(1), (2)
Figure
FCLK3
FCLK1
2–45:
FCLK0
FCLK2
(1), (2)
(1), (2)
(1), (2)
(1), (2)
FCLK7
FCLK5
FCLK6
FCLK4
(1), (2)
(1), (2)
Figure
Altera Corporation
2–46.
fclk[1..0]
July 2005