EP1S25F672C7N Altera, EP1S25F672C7N Datasheet - Page 166

• Manufacturer Part Number: EP1S25F672C7N
• Description: IC STRATIX FPGA 25K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S25F672C7N

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 473
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1858; EP1S25F672C7N

Stratix Automated Single Event Upset (SEU) Detection
Stratix
Automated
Single Event
Upset (SEU)
Detection
3–12
Stratix Device Handbook, Volume 1
Local Update Mode
Local update mode is a simplified version of the remote update. This
feature is intended for simple systems that need to load a single
application configuration immediately upon power up without loading
the factory configuration first. Local update designs have only one
application configuration to load, so it does not require a factory
configuration to determine which application configuration to use.
Figure 3–4
Figure 3–4. Local Update Transition Diagram
Stratix devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. FPGA devices that operate at high elevations
or in close proximity to earth’s North or South Pole require periodic
checks to ensure continued data integrity. The error detection cyclic
redundancy check (CRC) feature controlled by the Device & Pin Options
dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure
data reliability and is one of the best options for mitigating SEU.
nCONFIG
shows the transition diagram for local update mode.
Configuration
Error
or nCONFIG
Configuration
Configuration
Application
Power-Up
Factory
Configuration
Error
Altera Corporation
nCONFIG
July 2005