EP1S25F672C7N Altera, EP1S25F672C7N Datasheet - Page 272
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/74/67406/ep1s25f672c7n_sml.jpg)
EP1S25F672C7N
Manufacturer Part Number
EP1S25F672C7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1858
EP1S25F672C7N
EP1S25F672C7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672C7N
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP1S25F672C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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DLL Specifications
DLL
Specifications
4–102
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
t
ARESET
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2)
Symbol
See
PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output.
Use this equation (f
ranges to determine the allowed PLL settings.
When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
Refer to the section
This parameter is for high-speed differential I/O mode only.
These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
“Maximum Input & Output Clock Rates” on page
Tables 4–131
f
Minimum pulse width on
signal
through 4–133:
O U T
“High-Speed I/O Specification” on page 4–87
= f
Table 4–134
circuit.
For more information on DLL jitter, see the DDR SRAM section in the
Stratix Architecture chapter of the Stratix Device Handbook, Volume 1.
Table 4–135
across all PVT conditions. The Stratix DLL can be used below these
frequencies, but it will not achieve the full phase shift requested across all
I N
Parameter
Table 4–134. DLL Jitter for DQS Phase Shift Reference Circuit
* ml(n × post-scale counter)) in conjunction with the specified f
Frequency (MHz)
areset
reports the jitter for the DLL in the DQS phase shift reference
lists the Stratix DLL low frequency limit for full phase shift
197 to 200
160 to 196
100 to 159
4–76.
Min
10
for more information.
Max
DLL Jitter (ps)
± 100
± 300
± 500
Altera Corporation
I N P F D
January 2006
and f
V C O
Unit
ns
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