EP1S25F672C7N Altera, EP1S25F672C7N Datasheet - Page 267
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/74/67406/ep1s25f672c7n_sml.jpg)
EP1S25F672C7N
Manufacturer Part Number
EP1S25F672C7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1858
EP1S25F672C7N
EP1S25F672C7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672C7N
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP1S25F672C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
January 2006
t
t
t
t
t
t
t
f
t
t
f
% spread
t
f
f
f
f
t
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
LSKEW
SKEW
SS
ARESET
IN
INPFD
INDUTY
EINDUTY
INJITTER
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2)
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 1 of 3)
Symbol
Symbol
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
Time required to reconfigure the
scan chains for PLLs 5 and 6
Time required to reconfigure the
scan chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
(11)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Clock skew between two external
clock outputs driven by the same
counter
Clock skew between two external
clock outputs driven by the different
counters with the same settings
Spread spectrum modulation
frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
Input clock frequency
Input frequency to PFD
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
Parameter
Parameter
(10)
(5)
(11)
areset
(7)
(1),
Min
Min
300
0.5
(9)
40
40
45
10
30
10
3
3
(2)
Typ
±50
±75
Typ
±20 mUI for <200-MHz outclk
±100 ps for >200-MHz outclk
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
289/f
193/f
±200
600
Max
480
420
Max
100
400
150
60
60
0.6
55
22
SCANCLK
SCANCLK
(8)
(3)
MHz
MHz
Unit
ps or
MHz
MHz
Unit
mUI
kHz
ps
%
%
ps
ps
ns
μs
μs
%
%
4–97
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