EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 26
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 5 of 9)
April 2011 Altera Corporation
Receiver buffer and
CDR offset cancellation
time (per channel)
Programmable DC gain
EyeQ Data Rate
AEQ Data Rate
Decision Feedback
Equalizer (DFE) Data
Rate
Transmitter
Supported I/O
Standards
Data rate (Single width,
non-PMA Direct)
Data rate (Double
width, non-PMA Direct)
Data rate (Single width,
PMA Direct)
Data rate (Double
width, PMA Direct)
V
Differential on-chip
termination resistors
(12)
OCM
Description
Symbol/
outer envelope =
outer envelope =
DC Gain Setting
DC Gain Setting
DC Gain Setting
DC Gain Setting
DC Gain Setting
600 mV 8B/10B
0.65 V setting
150-Ω setting
100− Ω setting
120− Ω setting
encoded data
85− Ω setting
Conditions
(diff p-p)
(diff p-p)
500 mV
min V
min V
= 0
= 1
= 2
= 3
= 4
—
—
—
—
—
—
ID
ID
2500
3125
1000
1000
Min
600
600
600
—
—
—
—
—
—
—
–2 Commercial
Speed Grade
100 ± 15%
120 ± 15%
150 ± 15%
85 ± 15%
650
Typ
—
12
—
—
—
—
—
—
—
0
3
6
9
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
18500
3250
6500
6500
3750
8500
3250
6500
Max
—
—
—
—
—
—
1.4 V PCML, 1.5 V PCML
2500
3125
1000
1000
Min
600
Commercial/Industrial
600
600
—
—
—
—
—
—
—
Speed Grade
–2× Commercial
100 ± 15%
120 ± 15%
150 ± 15%
85 ± 15%
650
Typ
—
12
—
—
—
—
—
—
—
and
0
3
6
9
–3
18500
(1)
3250
6500
6500
Max
3750
6500
3250
6500
—
—
—
—
—
—
1000
1000
Commercial/Industrial
Min
600
600
600
—
—
—
—
—
—
—
—
—
Speed Grade
100 ± 15%
120 ± 15%
150 ± 15%
85 ± 15%
650
Typ
—
12
—
—
—
—
—
—
—
–4
0
3
6
9
1–18
18500
3250
Max
3750
6375
3250
6375
(22)
—
—
—
—
—
—
—
—
recon
cycles
Mbps
Mbps
Mbps
fig_
Mbps
Mbps
Mbps
Mbps
Unit
clk
mV
dB
dB
dB
dB
dB
Ω
Ω
Ω
Ω