XC5VLX30-1FF676C Xilinx Inc, XC5VLX30-1FF676C Datasheet - Page 106

• Manufacturer Part Number: XC5VLX30-1FF676C
• Description: IC FPGA VIRTEX-5 30K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-1FF676C

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA, FCBGA
• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 30720
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 400
• Ram Bits: 1179648
• For Use With: HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Phase-Locked Loops (PLLs)
106
Zero Delay Buffer
PLL with Internal Feedback
The PLL feedback can be internal to the PLL when the PLL is used as a synthesizer or jitter
filter and there is no required phase relationship between the PLL input clock and the PLL
output clock. The PLL performance should increase since the feedback clock is not
subjected to noise on the core supply since it never passes through a block powered by this
supply. Of course, noise introduced on the CLKIN signal and the BUFG will still be present
(Figure
X-Ref Target - Figure 3-11
The PLL can also be used to generate a zero delay buffer clock. A zero delay buffer can be
useful for applications where there is a single clock signal fan out to multiple destinations
with a low skew between them. This configuration is shown in the
feedback signal drives off chip and the board trace feedback is designed to match the trace
to the external components. In this configuration, it is assumed that the clock edges are
aligned at the input of the FPGA and the input of the external component. There will be a
limitation on the maximum delay allowed in the feedback path.
X-Ref Target - Figure 3-12
3-11).
IBUFG
IBUFG
Figure 3-11: PLL with Internal Feedback
CLKIN1
CLKFBIN
RST
PLL
www.xilinx.com
Inside FPGA
Figure 3-12: Zero Delay Buffer
CLKFBOUT
CLKIN1
CLKFBIN
RST
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
PLL
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
BUFG
BUFG
BUFG
OBUF
UG190_3_11_040906
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
To Logic
Figure
UG190_3_12_120108
3-12. Here, the
To
External
Components