XC5VLX30-1FF676C Xilinx Inc, XC5VLX30-1FF676C Datasheet - Page 208

• Manufacturer Part Number: XC5VLX30-1FF676C
• Description: IC FPGA VIRTEX-5 30K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-1FF676C

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA, FCBGA
• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 30720
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 400
• Ram Bits: 1179648
• For Use With: HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
Table 5-9: Slice SRL Timing Parameters
208
Sequential Delays for a Slice LUT Configured as an SRL
Setup and Hold Times for a Slice LUT Configured SRL
Notes:
1. This parameter includes a LUT configured as a two-bit shift register.
2. T
3. Parameter includes AI/BI/CI/DI configured as a data input (DI2) or two bits with a common shift.
T
T
T
T
T
REG
REG_MUX
REG_M31
WS
DS
XXCK
/T
/T
(1)
DH
WH
= Setup Time (before clock edge), and T
(3)
(1)
Parameter
Slice SRL Timing Parameters
Slice SRL Timing Characteristics
Table 5-9
Figure
Figure 5-30
Virtex-5 FPGA slice (a LUT configured as an SRL).
X-Ref Target - Figure 5-30
(MC31/DMUX)
Write Enable
Shift_In (DI)
(A/B/C/D)
(A/B/C/D)
Data Out
Address
5-29.
(WE)
MSB
CLK
shows the SLICEM SRL timing parameters for a majority of the paths in
CLK to A/B/C/D outputs
CLK to AMUX - DMUX output Time after the CLK of a write operation that the
CLK to DMUX output via
MC31 output
CE input (WE)
AX/BX/CX/DX configured as
data input (DI)
illustrates the timing characteristics of a 16-bit shift register implemented in a
X
X
CKXX
1
Figure 5-30: Slice SRL Timing Characteristics
Function
0
= Hold Time (after clock edge).
T
T
T
WS
DS
T
www.xilinx.com
REG
REG
0
X
0
2
(2)
1
X
1
3
Time after the CLK of a write operation that the
data written to the SRL is stable on the A/B/C/D
outputs of the slice.
data written to the SRL is stable on the DMUX
output of the slice.
Time after the CLK of a write operation that the
data written to the SRL is stable on the DMUX
output via MC31 output.
Time before/after the clock that the write enable
signal must be stable at the WE input of the slice
LUT (configured as an SRL).
Time before the clock that the data must be stable
at the AX/BX/CX/DX input of the slice
(configured as an SRL).
1
1
T
X
ILO
0
4
0
2
X
1
Description
5
1
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
1
ILO
X
0
6
1
0
1
X
ug190_5_30_050506
32
0