XC4VFX20-11FFG672C Xilinx Inc, XC4VFX20-11FFG672C Datasheet - Page 117

no-image

XC4VFX20-11FFG672C

Manufacturer Part Number
XC4VFX20-11FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX20-11FFG672C

Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Total Ram Bits
1253376
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX20-11FFG672C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX20-11FFG672C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX20-11FFG672C
Manufacturer:
XILINX
0
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Table 4-1: Dual-Port Names and Descriptions
Notes:
1. The
SSR[A|B]
CLK[A|B]
DO[A|B]
DOP[A|B]
DI[A|B]
DIP[A|B]
ADDR[A|B]
WE[A|B]
EN[A|B]
REGCE[A|B]
CASCADEIN[A|B]
CASCADEOUT[A|B]
“Data Parity Buses - DIP[A/B] and DOP[A/B]”
Port Name
(1)
(1)
www.xilinx.com
Figure 4-1: Dual-Port Data Flows
CASCADEOUTA
CASCADEINA
Data Input Bus
Data Input Parity Bus
Address Bus
Write Enable
When inactive no data is written to the block RAM and the
output bus remains in its previous state.
Set/Reset
Clock Input
Data Output Bus
Data Output Parity Bus
Output Register Enable
Cascade input pin for 32K x 1 mode
Cascade output pin for 32K x 1 mode
DIA
DIPA
ADDRA
WEA
ENA
SSRA
REGCEA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
REGCEB
CLKA
CLKB
18-Kbit Block RAM
Synchronous Dual-Port and Single-Port RAMs
Memory
Port A
Port B
18 Kb
Array
CASCADEOUTB
section has more information on Data Parity pins.
CASCADEINB
DOPA
DOPB
DOA
DOB
Description
ug070_4_01_071204
117

Related parts for XC4VFX20-11FFG672C