XC4VFX20-11FFG672C Xilinx Inc, XC4VFX20-11FFG672C Datasheet - Page 53

• Manufacturer Part Number: XC4VFX20-11FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-11FFG672C

• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Total Ram Bits: 1253376
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
BUFR VHDL and Verilog Templates
R
VHDL Template
Verilog Template
The following examples illustrate the instantiation of the BUFR module in VHDL and
Verilog.
--Example BUFR declaration
component BUFR
generic(
);
--Example BUFR instantiation
U_BUFR : BUFR
Port map (
--Declaring constraints in VHDL file
attribute BUFR_DIVIDE
attribute LOC : string;
attribute INIT_OUT of U_BUFR: label is BYPASS;
attribute LOC of U_BUFR: label is "BUFR_X#Y#";
--where # is valid integer locations of BUFR
//Example BUFR module declaration
module BUFR (O, CE, CLR, I);
endmodule;
//Example BUFR instantiation
BUFR U_BUFR (
.O(user_o),
.CE(user_ce),
.CLR(user_clr),
port(
end component;
);
O => user_o,
CE => user_ce,
CLR => user_clr,
I => user_i
);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
BUFR_DIVIDE
O: out std_ulogic;
CE: in
CLR: in
I: in
std_ulogic
std_ulogic;
std_ulogic;
www.xilinx.com
: string := "BYPASS";
: string;
VHDL and Verilog Templates
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