XC5VLX50T-2FF1136I Xilinx Inc, XC5VLX50T-2FF1136I Datasheet - Page 138

• Manufacturer Part Number: XC5VLX50T-2FF1136I
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FF1136I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 4: Block RAM
138
Block RAM Timing Model
Figure 4-15
This example takes the simplest paths on and off chip (these paths can vary greatly
depending on the design). This timing model demonstrates how and where the block
RAM timing parameters are used.
•
•
•
•
X-Ref Target - Figure 4-15
Synchronous
Write Enable
Set/Reset
NET = Varying interconnect delays
T
T
T
Address
IOPI
IOOP
BCCKO_O
Enable
Clock
Data
= Pad to I-output of IOB delay
= O-input of IOB to pad delay
illustrates the delay paths associated with the implementation of block RAM.
= BUFGCTRL delay
[T
[T
[T
[T
[T
[T
IOPI
IOPI
IOPI
IOPI
IOPI
IOPI
+ NET] + T
+ NET]
Figure 4-15: Block RAM Timing Model
+ NET] + T
+ NET] + T
[T
+ NET] + T
+ NET] + T
www.xilinx.com
BCCKO_O
BUFGCTRL
RCCK_ADDR
RCCK_WEN
RCCK_SSR
RCCK_EN
RDCK_DI
+ NET]
DI
ADDR
WE
EN
SSR
Block RAM
CLK
FPGA
DO
T
RCKO_DO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
+ [NET + T
IOOP
ug190_4_14_022207
]
Data