XC5VLX50T-2FF1136I Xilinx Inc, XC5VLX50T-2FF1136I Datasheet - Page 348

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-2FF1136I

Manufacturer Part Number
XC5VLX50T-2FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FF1136I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-2FF1136I
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC5VLX50T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-2FF1136I
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-2FF1136I
Quantity:
156
Chapter 7: SelectIO Logic Resources
348
ODDR VHDL and Verilog Templates
OLOGIC Timing Models
Timing Characteristics
The Libraries Guide includes templates for instantiation of the ODDR module in VHDL
and Verilog.
This section discusses all timing models associated with the OLOGIC block.
describes the function and control signals of the OLOGIC switching characteristics in the
Virtex-5 FPGA Data Sheet.
Table 7-15: OLOGIC Switching Characteristics
Figure 7-26
X-Ref Target - Figure 7-26
Setup/Hold
T
T
T
T
T
Clock to Out
T
T
OCE
CLK
ODCK
OOCECK
OSRCK
OTCK
OTCECK
OCKQ
RQ
OQ
SR
D1
/T
Symbol
/T
/T
/T
/T
OCKT
OCKD
OCKSR
illustrates the OLOGIC output register timing.
Figure 7-26: OLOGIC Output Register Timing Characteristics
OCKTCE
OCKOCE
1
T
T
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
ODCK
OOCECK
www.xilinx.com
T
OCKQ
2
Description
3
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
OSRCK
Table 7-15
ug190_7_21_041206
5

Related parts for XC5VLX50T-2FF1136I