XC5VLX50T-2FF1136I Xilinx Inc, XC5VLX50T-2FF1136I Datasheet - Page 155

• Manufacturer Part Number: XC5VLX50T-2FF1136I
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FF1136I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Case 4: Reading From An Empty or Almost Empty FIFO
There is minimum time between a rising read-clock and write-clock edge to guarantee that
AFULL will be deasserted. If this minimum is not met, the deassertion of AFULL can take
an additional write clock cycle.
Prior to the operations performed in
this example, the timing diagram reflects standard mode. For FWFT mode, data at DO
appears one read-clock cycle earlier.
X-Ref Target - Figure 4-24
Clock Event 1: Read Operation and Assertion of Almost EMPTY Signal
During a read operation to an almost empty FIFO, the Almost EMPTY signal is asserted.
•
•
•
Clock Event 2: Read Operation and Assertion of EMPTY Signal
The EMPTY signal pin is asserted when the FIFO is empty.
•
•
•
In the event that the FIFO is empty and a write followed by a read is performed, the
EMPTY signal remains asserted.
AEMPTY
WRCLK
RDERR
EMPTY
RDCLK
WREN
RDEN
Figure 4-24: Reading From an Empty / Almost Empty FIFO (Standard Mode)
At time T
RDEN input of the FIFO.
At time T
outputs of the FIFO.
At time T
asserted at the AEMPTY output pin of the FIFO.
Read enable remains asserted at the RDEN input of the FIFO.
At time T
the DO outputs of the FIFO.
At time T
output pin of the FIFO.
DO
FCCK_RDEN
FCKO_DO
FCKO_AEMPTY
FCKO_DO
FCKO_EMPTY
1
T
FCCK_RDEN
, after clock event 1 (RDCLK), data 00 becomes valid at the DO
, after clock event 2 (RDCLK), data 04 (last data) becomes valid at
00
T
, before clock event 1 (RDCLK), read enable becomes valid at the
FCKO_DO
, after clock event 2 (RDCLK), Empty is asserted at the EMPTY
www.xilinx.com
, one clock cycle after clock event 1 (RDCLK), Almost Empty is
01
T
FCKO_AEMPTY
Figure
T
FCKO_EMPTY
T
02
FCKO_DO
4-24, the FIFO is almost completely empty. In
T
FCKO_RDERR
FIFO Timing Models and Parameters
03
2
04
3
T
FCKO_RDERR
4
ug190_4_21_032506
T
FCCK_RDEN
155