XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 13
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-3FF1136C
Manufacturer Part Number
XC5VSX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-3FF1136C
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX50T-3FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 13 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Block RAM Initialization in VHDL or Verilog Code
Additional RAMB18 and RAMB36 Primitive Design Considerations
Additional Block RAM Primitives
Block RAM Applications
Block RAM Timing Model
Block RAM Retargeting
Built-in FIFO Support
FIFO Architecture: a Top-Level View
FIFO Primitives
FIFO Port Descriptions
FIFO Operations
FIFO Attributes
FIFO VHDL and Verilog Templates
Output Latches Initialization - INIT (INIT_A or INIT_B) . . . . . . . . . . . . . . . . . . . . . . 129
Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B]) . . . . . . . . . . . . . 130
Optional Output Register On/Off Switch - DO[A|B]_REG . . . . . . . . . . . . . . . . . . . . 130
Extended Mode Address Determinant - RAM_EXTENSION_[A|B] . . . . . . . . . . . . 130
Read Width - READ_WIDTH_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Write Width - WRITE_WIDTH_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Write Mode - WRITE_MODE_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Block RAM Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Independent Read and Write Port Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
RAMB18 and RAMB36 Port Mapping Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Cascadable Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Byte-wide Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Creating Larger RAM Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Block RAM SSR in Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Block RAM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Block RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Block RAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Multirate FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Synchronous FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
FIFO Almost Full/Empty Flag Offset Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Clock Event 1
Clock Event 2
Clock Event 4
Clock Event 5
Synchronous FIFO Implementations
Standard Mode
First Word Fall Through (FWFT) Mode
Empty Flag
Almost Empty Flag
Read Error Flag
Full Flag
Write Error Flag
Almost Full Flag
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
www.xilinx.com
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
. . . . . . . . . . . . . . . . . . . . . . . . 131
. . . . . . . . 131
13
Related parts for XC5VSX50T-3FF1136C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![XC5VSX50T-1FFG1136C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-1FF1136C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-1FFG665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-1FFG665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-2FF665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-2FFG665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-2FF1136C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-2FFG1136C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-1FF665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-1FF1136I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-1FFG1136I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-2FF665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-2FFG665I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-3FF665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VSX50T-3FFG665C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet: