XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 50
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XC5VSX50T-3FF1136C
Manufacturer Part Number
XC5VSX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-3FF1136C
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number
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Company:
Part Number:
XC5VSX50T-3FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 2: Clock Management Technology
DCM Primitives
50
DCM_BASE Primitive
The DCM primitives DCM_BASE and DCM_ADV are shown in
X-Ref Target - Figure 2-2
The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies
the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting
features are available to use with DCM_BASE.
DCM_BASE primitive.
Table 2-2: DCM_BASE Primitive
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Available Ports
CLKIN
CLKFB
RST
DCM_BASE
www.xilinx.com
CLKFX180
CLK2X180
LOCKED
CLKIN, CLKFB
RST
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED
CLK180
CLK270
CLKDV
CLK2X
CLKFX
CLK90
Figure 2-2: DCM Primitives
CLK0
Table 2-2
CLKIN
CLKFB
RST
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
Port Names
DCM_ADV
lists the available ports in the
CLKFX180
CLK2X180
PSDONE
LOCKED
DO[15:0]
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
Figure
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DRDY
CLK0
ug190_2_02_042706
2-2.
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