XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 34
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-3FF1136C
Manufacturer Part Number
XC5VSX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-3FF1136C
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX50T-3FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
34
X-Ref Target - Figure 1-9
In
•
•
•
•
•
•
BUFGMUX_1 is rising edge sensitive and held at High prior to input switch.
illustrates the timing diagram for BUFGMUX_1. A LOC constraint is available for
BUFGMUX and BUFGMUX_1.
X-Ref Target - Figure 1-10
In
•
•
•
•
•
•
Figure
Figure
The current clock is I0.
S is activated High.
If I0 is currently High, the multiplexer waits for I0 to deassert Low.
Once I0 is Low, the multiplexer output stays Low until I1 transitions High to Low.
When I1 transitions from High to Low, the output switches to I1.
If Setup/Hold are met, no glitches or short pulses can appear on the output.
The current clock is I0.
S is activated High.
If I0 is currently Low, the multiplexer waits for I0 to be asserted High.
Once I0 is High, the multiplexer output stays High until I1 transitions Low to High.
When I1 transitions from Low to High, the output switches to I1.
If Setup/Hold are met, no glitches or short pulses can appear on the output.
I 0
I1
O
S
1-9:
1-10:
Figure 1-10: BUFGMUX_1 Timing Diagram
I0
Figure 1-9: BUFGMUX Timing Diagram
I1
S
O
T
www.xilinx.com
BCCKO_O
switching using I1
T
BCCKO_O
begin
T
BCCCK_CE
T
BCCCK_CE
T
BCCKO_O
ug190_1_10_032306
ug190_1_09_032306
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Figure 1-10
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