XC5VLX110-2FF1760C Xilinx Inc, XC5VLX110-2FF1760C Datasheet - Page 223
![IC FPGA VIRTEX-5 110K 1760FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110-2FF1760C
Manufacturer Part Number
XC5VLX110-2FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-2FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-2FF1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Xilinx DCI
•
DCI uses two multi-purpose reference pins in each bank to control the impedance of the
driver or the parallel termination value for all of the I/Os of that bank. The N reference pin
(VRN) must be pulled up to V
must be pulled down to ground by another reference resistor. The value of each reference
resistor should be equal to the characteristic impedance of the PC board traces, or should
be twice that value. See
When a DCI I/O standard is used on a particular bank, the two multi-purpose reference
pins cannot be used as regular I/Os. However, if DCI I/O standards are not used in the
bank, these pins are available as regular I/O pins. The Virtex-5 Family Packaging
Specifications gives detailed pin descriptions.
DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or
off. The impedance is adjusted to match the external reference resistors. The impedance
adjustment process has two phases. The first phase compensates for process variations by
controlling the larger transistors in the I/Os. It occurs during the device startup sequence.
The second phase maintains the impedance in response to temperature and supply voltage
changes by controlling the smaller transistors in the I/Os. It begins immediately after the
first phase and continues indefinitely, even while the device is operating. By default, the
DONE pin does not go High until the first phase of the impedance adjustment process is
complete.
The coarse impedance calibration during the first phase of impedance adjustment can be
invoked after configuration by instantiating the DCIRESET primitive. By toggling the RST
input to the DCIRESET primitive while the device is operating, the DCI state machine is
reset and both phases of impedance adjustment proceed in succession. All I/Os using DCI
will be unavailable until the LOCKED output from the DCIRESET block is asserted.
This functionality is useful in applications where the temperature and/or supply voltage
changes significantly from device power-up to the nominal operating condition. Once at
the nominal operating temperature and voltage, performing the first phase of impedance
adjustment allows optimal headroom for the second phase of impedance adjustment.
For controlled impedance output drivers, the impedance can be adjusted either to match
the reference resistors or half the resistance of the reference resistors. For on-chip
termination, the termination is always adjusted to match the reference resistors.
DCI can configure output drivers to be the following types:
1.
2.
It can also configure inputs to have the following types of on-chip terminations:
1.
2.
For bidirectional operation, both ends of the line can be DCI-terminated regardless of
direction:
with X0Y199 and ends with X0Y160. This indicates that bank 13 is to the south of bank
11, and bank 15 is to the north. As the Y coordinates of these two banks are
consecutive, these two banks are considered consecutive banks and can be DCI
cascaded. It is possible to cascade through an unbonded bank.
DCI cascade is enabled by using the DCI_CASCADE constraint described in the
constraints guide.
Controlled Impedance Driver (Source Termination)
Controlled Impedance Driver with Half Impedance (Source Termination)
Input termination to V
Input termination to V
Driver with Termination to V
www.xilinx.com
CCO
CCO
CCO
/2 (Split Termination, Thevenin equivalent)
(Single Termination)
by a reference resistor, and the P reference pin (VRP)
SelectIO Resources General Guidelines
CCO
/2 (Split Termination), page
228.
223
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