XC5VLX110-2FF1760C Xilinx Inc, XC5VLX110-2FF1760C Datasheet - Page 32
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XC5VLX110-2FF1760C
Manufacturer Part Number
XC5VLX110-2FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-2FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-2FF1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
32
BUFGCE and BUFGCE_1
Unlike BUFG, BUFGCE is a clock buffer with one clock input, one clock output and a clock
enable line. This primitive is based on BUFGCTRL with some pins connected to logic High
or Low.
constraint is available for BUFGCE and BUFGCE_1.
X-Ref Target - Figure 1-5
The switching condition for BUFGCE is similar to BUFGCTRL. If the CE input is Low prior
to the incoming rising clock edge, the following clock pulse does not pass through the
clock buffer, and the output stays Low. Any level change of CE during the incoming clock
High pulse has no effect until the clock transitions Low. The output stays Low when the
clock is disabled. However, when the clock is being disabled it completes the clock High
pulse.
Since the clock enable line uses the CE pin of the BUFGCTRL, the select signal must meet
the setup time requirement. Violating this setup time may result in a glitch.
illustrates the timing diagram for BUFGCE.
X-Ref Target - Figure 1-6
BUFGCE_1 is similar to BUFGCE, with the exception of its switching condition. If the CE
input is Low prior to the incoming falling clock edge, the following clock pulse does not
pass through the clock buffer, and the output stays High. Any level change of CE during
the incoming clock Low pulse has no effect until the clock transitions High. The output
stays High when the clock is disabled. However, when the clock is being disabled it
completes the clock Low pulse.
BUFGCE(CE)
BUFGCE(O)
BUFGCE(I)
Figure 1-5
CE
I
illustrates the relationship of BUFGCE and BUFGCTRL. A LOC
Figure 1-6: BUFGCE Timing Diagram
Figure 1-5: BUFGCE as BUFGCTRL
BUFGCE
www.xilinx.com
T
BCCKO_O
O
T
BCCCK_CE
GND
GND
GND
V
V
V
CE
DD
DD
DD
BUFGCE as BUFGCTRL
I
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
ug190_1_05_032206
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_06_032206
O
Figure 1-6
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