XC5VLX110-2FF1760C Xilinx Inc, XC5VLX110-2FF1760C Datasheet - Page 86
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XC5VLX110-2FF1760C
Manufacturer Part Number
XC5VLX110-2FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-2FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-2FF1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 2: Clock Management Technology
X-Ref Target - Figure 2-19
86
PSINCDEC
PSDONE
PSCLK
CLKIN
PSEN
CLK0
Variable-Phase Shifting
D.C.
In
adjustments in the synchronous user interface. The PSDONE signal is asserted for one
cycle when the DCM completes one phase adjustment. After PSDONE is deasserted, PSEN
can be asserted again, allowing an additional phase shift to occur.
As shown in
synchronous to the rising edge of PSCLK.
•
•
1
Figure
Clock Event 1
At T
exactly one clock period; otherwise, a single increment/decrement of phase shift is not
guaranteed. Also, the PSINCDEC value at T
determines whether it is an increment (logic High) or a decrement (logic Low).
Clock Event 2
At T
or decrement of the DCM outputs. PSDONE is High for exactly one clock period when
the phase shift is complete. The time required for a complete phase shift varies. As a
result, PSDONE must be monitored for phase-shift status.
T
T
DMCCK_PSEN
DMCKO_PSDONE
Figure 2-19: Phase Shift Example: Variable
DMCCK_PSEN
DMCCK_PSINCDEC
2-19, the CLK0 output is phase-shifted using the dynamic phase-shift
Figure
2-19, all the variable-phase shift control and status signals are
, before clock event 1, PSEN is asserted. PSEN must be active for
, after clock event 2, PSDONE is asserted to indicate one increment
www.xilinx.com
D.C.
DMCCK_PSINCDEC
2
T
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DMCKO_PSDONE
, before clock event 1,
ug190_2_20_0042406
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