XC5VLX110-2FF1760C Xilinx Inc, XC5VLX110-2FF1760C Datasheet - Page 96
![IC FPGA VIRTEX-5 110K 1760FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110-2FF1760C
Manufacturer Part Number
XC5VLX110-2FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-2FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-2FF1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 3: Phase-Locked Loops (PLLs)
Table 3-3: PLL Ports
96
DADDR[4:0]
CLKINSEL
Pin Name
CLKFBIN
CLKIN1
CLKIN2
RST
PLL Ports
Determine the M and D Values
possible output frequencies for the second output frequency. Continue this process until all
the output frequencies are selected.
The constraints used to determine the allowed M and D values are shown in the following
equations:
Determining the input frequency can result in several possible M and D values. The next
step is to determine the optimum M and D values. The starting M value is first determined.
This is based off the VCO target frequency, the ideal operating frequency of the VCO.
The goal is to find the M value closest to the ideal operating point of the VCO. The
minimum D value is used to start the process. The goal is to make D and M values as small
as possible while keeping ƒ
Table 3-3
Input
Input
Input
Input
Input
Input
I/O
summarizes the PLL ports.
General clock input.
Secondary clock input to dynamically switch the PLL reference clock.
Feedback clock input.
Signal controls the state of the input mux, High = CLKIN1, Low = CLKIN2
Asynchronous reset signal. The RST signal is an asynchronous reset for the PLL. The
PLL will synchronously re-enable itself when this signal is released (i.e., PLL re-
enabled). A reset is required when the input clock conditions change (e.g.,
frequency).
The dynamic reconfiguration address (DADDR) input bus provides a
reconfiguration address for the dynamic reconfiguration. When not used, all bits
must be assigned zeros.
M
M
MAX
MIN
D
M
D
MAX
IDEAL
=
MIN
www.xilinx.com
=
rounddown
VCO
⎛
⎝
roundup
=
=
=
rounddown
as high as possible.
roundup
D
----------------------------------------------- -
MIN
Table 3-4
f
----------------------- -
VCOMIN
D
------------------------------------------------- -
×
f
MAX
Pin Description
------------------------ -
f
IN
f
PFD MAX
IN
f
VCOMAX
----------------------- -
f
PFD MIN
f
IN
×
lists the PLL attributes.
f
⎞
⎠
f
IN
IN
f
×
VCOMAX
D
MIN
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Equation 3-3
Equation 3-4
Equation 3-5
Equation 3-6
Equation 3-7
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