XC5VLX110-2FF1760C Xilinx Inc, XC5VLX110-2FF1760C Datasheet - Page 3
![IC FPGA VIRTEX-5 110K 1760FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110-2FF1760C
Manufacturer Part Number
XC5VLX110-2FF1760C
Description
IC FPGA VIRTEX-5 110K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-2FF1760C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-2FF1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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UG190 (v5.3) May 17, 2010
10/12/06
02/02/07
9/06/06
Date
Version
2.0
2.1
3.0
Added the LXT platform devices throughout document.
Chapter 1: Revised
Chapter 2: Updated
Chapter 4: Clarified the rules regarding FULL and EMPTY flags on
Chapter 5: Revised
Chapter 6:
and settings. Replaced the link to the SSO calculator.
Added System Monitor User Guide reference in the Preface.
Added XC5VLX85T to
Chapter 3: Revised
Chapter 4: Added cascade to
Removed scrub mode in
Chapter 5: Revised
Added the three SXT devices and the XC5VLX220T to
Chapter 4: Clarified wording in
Chapter 6: Added
in
Chapter 7: Revised OQ in
Chapter 8:
Table
6-39.
Differential Termination Attribute, page 237
Clock Enable Inputs - CE1 and CE2, page
DCI Cascading, page
Figure 1-22, page
Storage Elements, page
Figure
Figure 5-22, page
Output Clocks, page
www.xilinx.com
Table
Built-in Error Correction
Figure 7-27, page
3-1.
Table 4-7, page
1-5,
Synchronous Clocking, page
Table
45. Updated
197.
Revision
2-1, and
220. Changed V
65.
178.
349.
126. Revised ADDR in
Table
Clock Capable I/O, page
section.
356.
5-2.
Table
is updated for the latest syntax
REF
1-5,
for SSTL18_II_T_DCI to 0.9
119.
Virtex-5 FPGA User Guide
Table
Figure 4-9, page
page
2-1, and
139.
40.
Table
124.
5-2.
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